Research on high-linearity and high-speed readout circuit of ultra-large array infrared detector based on adaptive body-bias compensation and AC enhancement

Abstract:

In order to solve the problem of limited linearity and frame rate in the ultra-large array infrared (IR) detector readout process, this paper proposed a high-speed and high-linearity readout method. The readout circuit noise characteristics were optimized by adopting an efficient correlated double sampling (CDS) method within pixels, and the CDS voltage was output to the column bus. By employing an alternating current (AC) enhancement technique, the parasitic capacitance of the column bus was rapidly settled, while an adaptive body-bias compensation method was applied at the column bus termination to eliminate the nonlinearity introduced by the pixel source follower. A comprehensive experimental verification was conducted in the readout circuit of an 8 192 × 8 192 array IR detector based on the 55 nm process at a low temperature of 110 K. The results show that in comparison with a traditional readout circuit, the output swing is increased from 2 V to 3.3 V, and the full-well capacity is increased from 4.3 Me- to 6 Me-. The row time is reduced from 20 μs to 2 μs, and the linearity is improved from 96.9% to 99.98%. The overall power consumption of the chip is 1.6 W, and single column power consumption of the readout optimization circuit is 33 μW in the accelerated readout mode and 16.5 μW in the nonlinear correction mode.