Implementation to mitigate multi-bit upset in nano-scale SRAM

Abstract:

In order to solve the issue of multi-bit upset in nano-scale SRAM (processes below 100 nm) in aerospace applications, this study optimizes and improves traditional serial encoding and decoding methods based on multi-bit upset （MBU） characteristics of nano-scale SRAM. A parallel encoding and decoding approach is employed to implement a reinforcement method based on RS(2,8,4) code, enabling encoding and decoding outputs within one single clock cycle. The effectiveness of this reinforcement method in terms of delay and error correction capability is validated based on an FPGA platform. The test results show that, compared to the built-in Hamming code of Xilinx Block RAM, the proposed method has an equivalent output delay but with 5 to 8 times greater error detecting and correcting capability than those of Hamming code. Furthermore, when compared to encoding and decoding methods such as FUEC-QUAEC, CLC, the correction rate for consecutive 5-bit upset errors is elevated to 100%. Using parallel coding and decoding method, the implemented RS(2,8,4) code is effective for reinforcing multi-bit upset in nano-scale SRAM. At a minimum latency cost, it allows for the correction of any two symbols (up to 8 bits) within a single codeword (48 bits), fully correcting errors involving consecutive 5-bit upset within a single word in space radiation environment. The proposed MBU reinforcement method can be extended to external memory control interface or internal cache of CPUs addressing the issue of multi-bit upset errors in caches of existing aerospace processors that rely on single-error correction codes.