纳米级SRAM多位翻转检纠错方法实现

Implementation to mitigate multi-bit upset in nano-scale SRAM

摘要:

为解决纳米级SRAM（100 nm以内工艺）在航天工程应用中出现的多位翻转问题,依据纳米级SRAM的翻转特性,在传统串行编译码的基础上优化改进,采用并行编译码的方式,实现了基于RS(2,8,4)码的纳米级SRAM的加固方法,在单时钟节拍内实现编译码输出。以FPGA为平台,验证该加固方法的延时和纠错能力。测试结果表明:与Xilinx自带的可检二纠一汉明码的块RAM相比,本文提出的方法访问延时相近,但纠错能力是汉明码的5~8倍；与FUEC-QUAEC、CLC等编译码方法相比,将连续5 bit翻转错误的纠正率提高到100%。采用并行编译码实现的基于RS(2,8,4)码加固方法可用于纳米级SRAM抗多位翻转加固,以较小的延时代价实现纠正一个码字（48 bit）内任意两个符号（最多8 bit）内的错误,可完全纠正空间单粒子环境中出现的单个字内连续5 bit翻转的错误。该加固方法可扩展应用到CPU外部存储器的访问控制以及CPU内部cache的加固,以解决现有航天处理器采用检二纠一码无法纠正其cache多位翻转错误的问题。

Abstract:

In order to solve the issue of multi-bit upset in nano-scale SRAM (processes below 100 nm) in aerospace applications, this study optimizes and improves traditional serial encoding and decoding methods based on multi-bit upset （MBU） characteristics of nano-scale SRAM. A parallel encoding and decoding approach is employed to implement a reinforcement method based on RS(2,8,4) code, enabling encoding and decoding outputs within one single clock cycle. The effectiveness of this reinforcement method in terms of delay and error correction capability is validated based on an FPGA platform. The test results show that, compared to the built-in Hamming code of Xilinx Block RAM, the proposed method has an equivalent output delay but with 5 to 8 times greater error detecting and correcting capability than those of Hamming code. Furthermore, when compared to encoding and decoding methods such as FUEC-QUAEC, CLC, the correction rate for consecutive 5-bit upset errors is elevated to 100%. Using parallel coding and decoding method, the implemented RS(2,8,4) code is effective for reinforcing multi-bit upset in nano-scale SRAM. At a minimum latency cost, it allows for the correction of any two symbols (up to 8 bits) within a single codeword (48 bits), fully correcting errors involving consecutive 5-bit upset within a single word in space radiation environment. The proposed MBU reinforcement method can be extended to external memory control interface or internal cache of CPUs addressing the issue of multi-bit upset errors in caches of existing aerospace processors that rely on single-error correction codes.